Yiorgos Makris
Assistant Professor of Electrical Engineering & Computer Science

Dipl. Eng., University of Patras, Greece, 1995
M.S., Ph.D., University of California, San Diego, 1997, 2001
Joined Yale Faculty 2001
Personal Homepage

Makris’ research interests are in the areas of Digital Systems Testing, Design for Testability, Computer-Aided-Design, Fault Tolerance, Validation, and Design Diagnosis. His work targets Register-Transfer-Level descriptions and focuses on hierarchical methods for identifying and utilizing transparency behavior in support of reliable integrated circuit design. Yiorgos devised a Register-Transfer-Level Testability Analysis methodology for hierarchical designs based on the concept of transparency channels, an innovative mechanism for expressing fine-grained design traversal capabilities. He designed and led the implementation effort for TRANSPARENT, a prototype tool that implements this methodology and he further investigated the effectiveness of Testability Analysis data in guiding Design-for-Test (DFT) and Synthesis-for-Test (SFT) approaches. Additionally, he explored the applicability of transparent paths in Hierarchical Test Generation, On-line Test, and Design Diagnosis. In his current research, Yiorgos is examining concurrent test methods for Analog and Digital Circuits, design and test of Asynchronous Circuits and new ideas in Test Generation.

Representative Publications:
	"Invariance-Based On-Line Test for RTL Controller-Datapath Circuits," with I. Bayraktaroglu and A. Orailoglu, Proceedings of the IEEE VLSI Test Symposium, pp. 459-464, 2000.
	"TRANSPARENT: A System for RTL Testability Analysis, DFT Guidance and Hierarchical Test Generation," with J. Collins, A. Orailoglu, and P. Vishakantaiah, Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 159-162, 1999.
	"RTL Test Justification and Propagation Analysis for Modular Designs," with A. Orailoglu, Journal of Electronic Testing: Theory & Applications, Kluwer Academic Publishers, 13(2):105-120, 1998.