Home Problem Statement
TCP/IP protocol processing latency has been an important issue in high-speed networks.
Interesting Results
We conduct an architectural study of TCP/IP protocol. We port the TCP/IP protocol stack from the 4.4 FreeBSD to the SimpleScalar simulation environment.
We first study the architectural characteristics, such as instruction level parallelism and cache behaviors, through simulation. We also compare the characteristics of TCP/IP protocol to that of SPECint benchmark programs. It turns out that the former is quite different from the latter due to the unique processing structure. Furthermore, in order to improve the effectiveness of instruction cache, frequent instruction pairs are analyzed, and corresponding architectural optimizations are made to the instruction set architecture. We find that a 23% improvement can be achieved by taking advantage of the optimization. The instruction set optimizations proposed in this paper will be helpful for the design of new programmable protocol processors in future.
Paper Toys
- Architectural Analysis and Instruction-Set Optimization for Design of Network Protocol Processors , Haiyong Xie, Li Zhao, and Laxmi Bhuyan. In Proceedings of The First IEEE/ACM/IFIP International Conference on HW/SW Codesign and System Synthesis (CODES+ISSS 2003), Newport Beach, California, October 2003. (PDF)